As the size of transistors has scaled down, so have many digital applications. Cell phones, laptops, sensors, and many other applications all shrunk in size over the last few decades and they are more and more portable. For this to happen, chips in these digital applications have to be designed to optimize the number of transistors used, the fewer the better. In this case, pass transistor logic is an attractive solution because a circuit can usually be implemented in pass transistor logics with around half of the number of transistors required for static CMOS implementation. However, pass transistor logic allows inputs to be tied to the source and the drain of a transistor, thus create possible situations where NMOS has to drive a logic 1 and PMOS has to drive a logic 0. Since NMOS is not a good pull-up device, the output of a pass transistor circuit will suffer from a voltage drop Vth and never achieve a full voltage swing to VDD. With the continuing scaling of supply voltage, this voltage drop cannot be tolerated.
FinFET is a double-gate field effect transistor (DGFET). By having two gates that can be independently controlled, FinFET is more versatile than traditional single-gate field effect transistors. The additional back gate of a FinFET gives circuit designers many options. The back gate can serve as a secondary gate that enhances the performances of the front (primary) gate. For example, if the front gate voltage is VDD (transistor is ON) the back gate can be biased to VDD to provide bigger current drive, which reduces transistor delay. If the front gate voltage is 0 (transistor is OFF), the back gate can be biased to 0, which raises the threshold voltage of the front gate and reduces the leakage current. Most recent FinFET circuit researches, such as FinFET SRAM (See A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. J. King Liu, and B. Nikolic, “FinFET SRAM with Enhanced Read/Write Margins”, SOI Conference, 2006), focus on utilizing the back gate to improve circuit performance. On the other hand, the back gate can also be used to reduce the number of transistors needed to implement many logic functions. For an N-type FinFET (N-FinFET), the transistor turns on if either the front gate or the back gate is VDD—this is equivalent to two NMOS transistors in parallel. Recent researches, such as a three-transistor FinFET NAND gate (A. Muttreja, N. Agarwal, N. K. Jha, “CMOS logic design with independent-gate FinFETs”, ICCD 25th International Conference, 2007, pp. 560-567), utilize this property. However, to our understanding, no research utilizes this property beyond a simple logic gate such as a NAND gate.